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3.3v 8k/16k x 9 synchronous dual port static ram cy7c09159av cy7c09169av cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-06053 rev. *b revised september 6, 2005 features ? true dual-ported memory cells which allow simulta- neous access of the same memory location ? two flow-through/pipelined devices ? 8k x 9 organization (cy7c09159av) ? 16k x 9 organization (cy7c09169av) ? three modes ? flow-through ? pipelined ?burst ? pipelined output mode on both ports allows fast 83-mhz operation ? 0.35-micron cmos fo r optimum speed/power ? high-speed clock to data access 9 and 12 ns (max.) ? 3.3v low operating power ? active = 135 ma (typical) ? standby = 10 a (typical) ? fully synchronous interface for easier operation ? burst counters increment addresses internally ? shorten cycle times ? minimize bus noise ? supported in flow-through and pipelined modes ? dual chip enables for easy depth expansion ? automatic power-down ? commercial and industrial temperature ranges ? available in 100-pin tqfp ? pb-free packages available notes: 1. a 0 ? a 12 for 8k; a 0 ? a 13 for 16k. logic block diagram r/w l ce 0l ce 1l oe l ft /pipe l i/o 0l ? i/o 8l control a 0 ? a 12/13l clk l ads l cnten l cntrst l r/w r 1 0 0/1 ce 0r ce 1r oe r 1 0/1 0 ft /pipe r i/o 0r ? i/o 8r i/o control a 0 ? a 12/13r clk r ads r cnten r cntrst r 1 0 0/1 1 0/1 0 i/o counter/ address register decode true dual-ported ram array counter/ address register decode 9 9 [1] [1] 13/14 13/14 cy7c09159av cy7c09169av3.3v 8k/16k x 9 synchronous dual port static ram [+] feedback
cy7c09159av cy7c09169av document #: 38-06053 rev. *b page 2 of 16 functional description the cy7c09159av and cy7c09169av are high-speed synchronous cmos 8k and 16k x 9 dual-port static rams. two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. [2] registers on control, address, and data lines allow for minimal set-up and hold times. in pipelined output mode, data is regis- tered for decreased cycle time. clock to data valid t cd2 = 9 ns (pipelined). flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. in flow-through mode data will be available t cd1 = 18 ns after the address is clocked into the device. pipelined output or flow-through mode is selected via the ft /pipe pin. each port contains a burst counter on the input address register. the internal write pulse width is independent of the low- to-high transition of the clock signal. the internal write pulse is self-timed to allow t he shortest possible cycle times. a high on ce 0 or low on ce 1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. the use of multiple chip enables allows easier banking of multiple chips for depth expansion configurations. in the pipelined mode, one cycle is required with ce 0 low and ce 1 high to reactivate the outputs. counter enable inputs are provided to stall the operation of the address input and utilize the inte rnal address generated by the internal counter for fast interleaved memory applications. a port?s burst counter is loaded with the port?s address strobe (ads ). when the port?s count enable (cnten ) is asserted, the address counter will increment on each low-to-high transition of that port?s clock signal. this will read/write one word from/into each successive address location until cnten is deasserted. the counter can address the entire memory array and will loop back to the start. counter reset (cntrst ) is used to reset the burst counter. all parts are available in 100-pin thin quad plastic flatpack (tqfp) packages. note: 2. when simultaneously writing to the same location, final value cannot be guaranteed. [+] feedback
cy7c09159av cy7c09169av document #: 38-06053 rev. *b page 3 of 16 pin configuration 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 nc nc a7r a8r a9r a10r nc a12r nc gnd nc nc ce 0r a13r a11r nc nc ce1r cntrst r r/wr oe r ft /piper gnd nc nc 58 57 56 55 54 53 52 51 cy7c09159av (8k x 9) nc nc a7l a8l a9l a10l nc a12l nc vcc nc nc ce 0l a13l a11l nc nc ce1l cntrst l r/w l oe l ft /pipel nc nc nc 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 nc nc a6l a5l a4l a3l clkl a1l cntenl gnd gnd cntenr a0r a0l a2l adsr clkr a1r a2r a3r a4r a5r a6r nc adsl 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 nc nc i/o8r i/o7r i/o6r i/o5r i/01r i/o3r i/o2r gnd vcc gnd i/o2l vcc i/o4r i/o0l i/o1l i/o3l i/o4l i/o5l i/o6l i/o7l i/o8l gnd i/o0r 33 32 31 30 29 28 27 26 cy7c09169av (16k x 9) 100-pin tqfp (top view) [3] [3] selection guide cy7c09159av cy7c09169av -9 cy7c09159av cy7c09169av -12 unit f max2 (pipelined) 67 50 mhz max access time (clock to data, pipelined) 9 12 ns typical operating current i cc 135 115 ma typical standby current for i sb1 (both ports ttl level) 20 20 ma typical standby current for i sb3 (both ports cmos level) 10 10 a note: 3. this pin is nc for cy7c09159av. [+] feedback
cy7c09159av cy7c09169av document #: 38-06053 rev. *b page 4 of 16 maximum ratings [4] (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature wit h power applied ..?55 c to +125 c supply voltage to ground potential ............... ?0.5v to +4.6v dc voltage applied to outputs in high z state...... ......................?0.5v to v cc +0.5v dc input voltage......................................?0.5v to v cc +0.5v output current into outputs (low)............................. 20 ma static discharge voltage......... .............. .............. ....... >2001v latch-up current ..................................................... >200 ma note: 4. the voltage on any input or i/o pin can not exceed the power pin during power-up 5. industrial parts are available in cy7c09169av only. pin definitions left port right port description a 0l ?a 13l a 0r ?a 13r address inputs (a 0 ? a 12 for 8k; a 0 ? a 13 for 16k devices). ads l ads r address strobe input. used as an address qualifie r. this signal should be asserted low during normal read or write transactions. asserting this signal low also loads the burst address counter with data present on the i/o pins. ce 0l ,ce 1l ce 0r ,ce 1r chip enable input. to select eith er the left or right port, both ce 0 and ce 1 must be asserted to their active states (ce 0 v il and ce 1 v ih ). clk l clk r clock signal. this input can be free-running or strobed. maximum clock input rate is f max . cnten l cnten r counter enable input. asserting this signal lo w increments the burst address counter of its respective port on each rising edge of clk. cnten is disabled if ads or cntrst are asserted low. cntrst l cntrst r counter reset input. asserting th is signal low resets the burst address counter of its respective port to zero. cntrst is not disabled by asserting ads or cnten . i/o 0l ?i/o 8l i/o 0r ?i/o 8r data bus input/output (i/o 0 ?i/o 7 for x8 devices; i/o 0 ?i/o 8 for x9 devices). oe l oe r output enable input. this signal must be asse rted low to enable the i/o data pins during read operations. r/w l r/w r read/write enable input. this signal is asserted lo w to write to the dual-port memory array. for read operations, assert this pin high. ft /pipe l ft /pipe r flow-through/pipelined select input. for flow-thr ough mode operation, assert this pin low. for pipelined mode operation, assert this pin high. gnd ground input. nc no connect. v cc power input. operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v 300 mv industrial [5] ?40 c to +85 c 3.3v 300 mv [+] feedback
cy7c09159av cy7c09169av document #: 38-06053 rev. *b page 5 of 16 note: 6. ce l and ce r are internal signals. to select either the left or right port, both ce 0 and ce 1 must be asserted to their active states (ce 0 v il and ce 1 v ih ). electrical characteristics over the operating range parameter description cy7c09159av cy7c09169av unit -9 -12 min. typ. max. min. typ. max. v oh output high voltage (v cc = min., i oh = ?4.0 ma) 2.4 2.4 v v ol output low voltage (v cc = min., i oh = +4.0 ma) 0.4 0.4 v v ih input high voltage 2.0 2.0 v v il input low voltage 0.8 0.8 v i oz output leakage current ?10 10 ?10 10 a i cc operating current (v cc = max., i out = 0 ma) outputs disabled com?l. 135 230 115 180 ma ind. [5] 155 250 ma i sb1 standby current (both ports ttl level) [6] ce l & ce r v ih , f = f max com?l. 20 75 20 70 ma ind. [5] 30 80 ma i sb2 standby current (one port ttl level) [6] ce l | ce r v ih , f = f max com?l. 95 155 85 140 ma ind. [5] 95 150 ma i sb3 standby current (both ports cmos level) [6] ce l & ce r v cc ? 0.2v, f = 0 com?l. 10 500 10 500 a ind. [5] 10 500 a i sb4 standby current (one port cmos level) [6] ce l | ce r v ih , f = f max com?l. 85 115 75 100 ma ind. [5] 85 110 ma capacitance parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 10 pf c out output capacitance 10 pf ac test loads (a) normal load (load 1) r1 = 590 ? 3 . 3v output r2 = 435 ? c = 30 pf v th = 1.4v output (b) thvenin equivalent (load 1) (c) three-state delay (load 2) 3.3v output r th = 250 ? (used for t cklz , t olz , & t ohz including scope and jig) c = 30 pf c = 5 pf r1 = 590 ? r2 = 435 ? [+] feedback
cy7c09159av cy7c09169av document #: 38-06053 rev. *b page 6 of 16 switching characteristics over the operating range parameter description cy7c09159av unit -9 -12 min. max. min. max. f max1 f max flow-through 40 33 mhz f max2 f max pipelined 67 50 mhz t cyc1 clock cycle time - flow-through 25 30 ns t cyc2 clock cycle time - pipelined 15 20 ns t ch1 clock high time - flow-through 12 12 ns t cl1 clock low time - flow-through 12 12 ns t ch2 clock high time - pipelined 6 8 ns t cl2 clock low time - pipelined 6 8 ns t r clock rise time 3 3 ns t f clock fall time 3 3 ns t sa address set-up time 4 4 ns t ha address hold time 1 1 ns t sc chip enable set-up time 4 4 ns t hc chip enable hold time 1 1 ns t sw r/w set-up time 4 4 ns t hw r/w hold time 1 1 ns t sd input data set-up time 4 4 ns t hd input data hold time 1 1 ns t sad ads set-up time 4 4 ns t had ads hold time 1 1 ns t scn cnten set-up time 4 4 ns t hcn cnten hold time 1 1 ns t srst cntrst set-up time 4 4 ns t hrst cntrst hold time 1 1 ns t oe output enable to data valid 10 12 ns t olz oe to low z 2 2 ns t ohz oe to high z 1 7 1 7 ns t cd1 clock to data valid - flow-through 20 25 ns t cd2 clock to data valid - pipelined 9 12 ns t dc data output hold after clock high 2 2 ns t ckhz clock high to output high z 2 9 2 9 ns t cklz clock high to output low z 2 2 ns port to port delays t cwdd write port clock high to read data delay 40 40 ns t ccs clock to clock set-up time 15 15 ns [+] feedback
cy7c09159av cy7c09169av document #: 38-06053 rev. *b page 7 of 16 switching waveforms read cycle for flow-through output (ft /pipe = v il ) [7, 8, 9, 10] read cycle for pipelined operation (ft /pipe = v ih ) [7, 8, 9, 10] notes: 7. oe is asynchronously controlled; all other i nputs are synchronous to the rising clock edge. 8. ads = v il , cnten and cntrst = v ih 9. the output is disabled (high-impedance state) by ce 0 =v ih or ce 1 = v il following the next rising edge of the clock. 10. addresses do not have to be a ccessed sequentially since ads = v il constantly loads the address on the rising edge of the clk. numbers are for reference only. t ch1 t cl1 t cyc1 t sc t hc t dc t ohz t oe t sc t hc t sw t hw t sa t ha t cd1 t ckhz t dc t olz t cklz a n a n+1 a n+2 a n+3 q n q n+1 q n+2 clk ce 0 ce 1 r/w address data out oe t ch2 t cl2 t cyc2 t sc t hc t sw t hw t sa t ha a n a n+1 clk ce 0 ce 1 r/w address data out oe a n+2 a n+3 t sc t hc t ohz t oe t olz t dc t cd2 t cklz q n q n+1 q n+2 1 latency [+] feedback
cy7c09159av cy7c09169av document #: 38-06053 rev. *b page 8 of 16 bank select pipelined read [11, 12] - left port write to flow-through right port read [13, 14, 15, 16] notes: 11. in this depth expansion example, b1 repr esents bank #1 and b2 is bank #2; each bank consists of one cypress dual-port device from this data sheet. address (b1) = address (b2) . 12. oe and ads = v il ; ce 1(b1) , ce 1(b2) , r/w , cnten , and cntrst = v ih . 13. the same waveforms apply for a right port write to flow-through left port read. 14. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . 15. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 16. it t ccs maximum specified, then data from right port read is not valid until the maximum specified for t cwdd . if t ccs >maximum specified, then data is not valid until t ccs + t cd1 . t cwdd does not apply in this case. switching waveforms (continued) d 3 d 1 d 0 d 2 a 0 a 1 a 2 a 3 a 4 a 5 d 4 a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha t sc t hc t sa t ha t sc t hc t sc t hc t sc t hc t ckhz t dc t dc t cd2 t cklz t cd2 t cd2 t ckhz t cklz t cd2 t ckhz t cklz t cd2 t ch2 t cl2 t cyc2 clk l address (b1) ce 0(b1) data out(b2) data out(b1) address (b2) ce 0(b2) t sa t ha t sw t hw t sd t hd match valid t ccs t sw t hw t dc t cwdd t cd1 match t sa t ha match no match no valid valid t dc t cd1 clk l r/w l address l data inl address r data outr clk r r/w r [+] feedback
cy7c09159av cy7c09169av document #: 38-06053 rev. *b page 9 of 16 pipelined read-to-write-to-read (oe = v il ) [10, 17, 18, 19] pipelined read-to-write-to-read (oe controlled) [10, 17, 18, 19] notes: 17. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 18. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . 19. during ?no operation,? data in memory at the selected address may be corrupted and should be rewritten to ensure data integr ity. switching waveforms (continued) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa t hw t sw t cd2 t ckhz t sd t hd t cklz t cd2 no operation write read read clk ce 0 ce 1 r/w address data in data out a n a n+1 a n+2 a n+2 d n+2 a n+3 a n+4 q n q n+3 t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa a n a n+1 a n+2 a n+3 a n+4 a n+5 t hw t sw t sd t hd d n+2 t cd2 t ohz read read write d n+3 t cklz t cd2 q n q n+4 clk ce 0 ce 1 r/w address data out data in oe [+] feedback
cy7c09159av cy7c09169av document #: 38-06053 rev. *b page 10 of 16 flow-through read-to-write-to-read (oe = v il ) [8, 10, 17, 18, 19] flow-through read-to-write-to-read (oe controlled) [8, 10, 17, 18, 19] switching waveforms (continued) t ch1 t cl1 t cyc1 t sc t hc t sw t hw t sa t ha t sw t hw t sd t hd a n a n+1 a n+2 a n+2 a n+3 a n+4 d n+2 q n q n+1 q n+3 t cd1 t cd1 t dc t ckhz t cd1 t cd1 t cklz t dc read no operation write read clk ce 0 ce 1 address r/w data in data out q n t ch1 t cl1 t cyc1 t sc t hc t sw t hw t sa t ha t cd1 t dc t ohz read a n a n+1 a n+2 a n+3 a n+4 a n+5 d n+2 d n+3 t sw t hw t sd t hd t cd1 t cd1 t cklz t dc q n+4 t oe write read clk ce 0 ce 1 address r/w data in data out oe [+] feedback
cy7c09159av cy7c09169av document #: 38-06053 rev. *b page 11 of 16 pipelined read with address counter advance [20] flow-through read with address counter advance [20] note: 20. ce 0 and oe = v il ; ce 1 , r/w and cntrst = v ih . switching waveforms (continued) counter hold read with counter t sa t ha t sad t had t scn t hcn t ch2 t cl2 t cyc2 t sad t had t scn t hcn q x-1 q x q n q n+1 q n+2 q n+3 t dc t cd2 read with counter read external address clk address ads data out cnten a n t ch1 t cl1 t cyc1 t sa t ha t sad t had t scn t hcn q x q n q n+1 q n+2 q n+3 a n t sad t had t scn t hcn t dc t cd1 counter hold read with counter read external address read with counter clk address ads data out cnten [+] feedback
cy7c09159av cy7c09169av document #: 38-06053 rev. *b page 12 of 16 write with address counter advance (flow-through or pipelined outputs) [21, 22] notes: 21. ce 0 and r/w = v il ; ce 1 and cntrst = v ih . 22. the ?internal address? is equal to the ?external address? when ads = v il and equals the counter output when ads = v ih . switching waveforms (continued) t ch2 t cl2 t cyc2 a n a n+1 a n+2 a n+3 a n+4 d n+1 d n+1 d n+2 d n+3 d n+4 a n d n t sad t had t scn t hcn t sd t hd write external write with counter address write with counter write counter hold clk address internal cnten ads data in address t sa t ha [+] feedback
cy7c09159av cy7c09169av document #: 38-06053 rev. *b page 13 of 16 counter reset (pipelined outputs) [10, 17, 23, 24] notes: 23. ce 0 = v il ; ce 1 = v ih . 24. no dead cycle exists during counter reset. a read or write cycle may be coincidental with the counter reset. switching waveforms (continued) t ch2 t cl2 t cyc2 clk address internal cnten ads data in address cntrst r/w data out q 0 q 1 q n d 0 a x 01a n a n+1 t sad t had t scn t hcn t srst t hrst t sd t hd t sw t hw a n a n+1 t sa t ha counter reset write address 0 read address 0 read address 1 read address n [+] feedback
cy7c09159av cy7c09169av document #: 38-06053 rev. *b page 14 of 16 notes: 25. ?x? = ?don?t care,? ?h? = v ih , ?l? = v il . 26. ads , cnten , cntrst = ?don?t care.? 27. oe is an asynchronous input signal. 28. when ce changes state in the pipelined mode, deselection and read happen in the following clock cycle. 29. ce 0 and oe = v il ; ce 1 and r/w = v ih . 30. data shown for flow-through mode; pipelined mode output will be delayed by one cycle. 31. counter operation is independent of ce 0 and ce 1 . read/write and enable operation [25, 26, 27] inputs outputs oe clk ce 0 ce 1 r/w i/o 0 ? i/o 9 operation x h x x high-z deselected [28] x x l x high-z deselected [28] x l h l d in write l l h h d out read [28] h x l h x high-z outputs disabled address counter control operation [25, 29, 30, 31] address previous address clk ads cnten cntrst i/o mode operation x x x x l d out(0) reset counter reset to address 0 a n x l x h d out(n) load address load into counter x a n h h h d out(n) hold external address blocked?counter disabled x a n h l h d out(n+1) increment counter enabled?internal address generation [+] feedback
cy7c09159av cy7c09169av document #: 38-06053 rev. *b page 15 of 16 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. ordering information all products and company names mentioned in this docum ent may be the trademarks of their respective holders. 8k x9 3.3v synchronous dual-port sram speed (ns) ordering code package name package type operating range 9 cy7c09159av-9ac a100 100-pin thin quad flat pack commercial cy7c09159av-9axc a100 100-pin pb-free thin quad flat pack 12 cy7c09159av-12ac a100 100-pin thin quad flat pack commercial cy7c09159av-12axc a100 100-pin pb-free thin quad flat pack 16k x9 3.3v synchronous dual-port sram speed (ns) ordering code package name package type operating range 9 cy7c09169av-9ac a100 100-pin thin quad flat pack commercial 12 cy7c09169av-12ac a100 100-pin thin quad flat pack commercial CY7C09169AV-12AXC a100 100-pin pb-free thin quad flat pack cy7c09169av-12ai a100 100-pin thin quad flat pack industrial cy7c09169av-12axi a100 100-pin pb-free thin quad flat pack package diagram 100-pin thin plastic quad flat pack (tqfp) a100 51-85048-*b 100-pin pb-free thin plastic quad flat pack (tqfp) a100 [+] feedback
cy7c09159av cy7c09169av document #: 38-06053 rev. *b page 16 of 16 document history page document title: cy7c09159av/cy7c09169av 3.3v 8k/16k x 9 synchronous dual port sram document number: 38-06053 rev. ecn no. issue date orig. of change description of change ** 110205 11/15/01 szv change from spec number: 38-00839 to 38-06053 *a 122303 12/27/02 rbi power up requirements added to maximum ratings information *b 393581 see ecn yim added pb-free logo added pb-free parts to ordering information: cy7c09159av-9axc, cy7c09159av-12axc, CY7C09169AV-12AXC, cy7c09169av-12axi [+] feedback

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